Interleavers (block or convolutional) are popular techniques for protecting data from noise in data transmission systems, such as SDH and PDH radio systems, GSM and UMTS mobile communication systems, and point-to-multipoint radio systems. Interleaver techniques are also used in conjunction with data scramblers (synchronous and asynchronous), check codes, error correction codes (e.g., Reed-Solomon, Viterbi, BCH), and are used to control impulse noise. Convolutional interleavers are often used in conjunction with Viterbi or Reed-Solomon codecs, since the load is dramatically reduced after the de-interleaver stage. Convolutional interleavers are conceptually similar to block interleavers, although they are more complex to implement. Convolutional interleavers are area efficient, using only half the density needed by block interleavers.
On the transmit side of a data transmission system, a convolutional interleaver is often used to parallelize serial input data into N-bit words and shift the data word through N delay lines. The delayed data is then shifted out through a parallel-in-serial-out (PISO) shift register for transmission. At the receiver, the incoming data stream is reconstructed with dual delay lines and shift registers.
The heart of a convolutional interleaver is a set of progressive delay lines. Delay lines in conventional interleavers use flip-flops, which are register-intensive, and consume relatively scarce silicon resources. Convolutional interleavers have been developed for use with field-programmable gate array (FPGA) devices that use multi-port memory, such as dual-port static random access memory (SRAM) and progressive delay lines that save logic resources and produce highest performance. Block SRAM (BRAM) resources are typically used in many applications running on an FPGA, and multi-port BRAM is a highly utilized resource. Implementations of convolutional interleavers have been built using external memory resources, such as external SRAM chips, which mimic on-chip BRAM of FPGAs, and are relatively easily incorporated into existing convolutional interleaver algorithms. External memory techniques are especially desirable for use in larger interleavers, where using on-chip memory resources might compromise other applications. However, the cost of SRAM chips is relatively high compared to other types of memory and conventional convolutional interleavers do not efficiently use memories that can operate in burst modes.
Convolutional interleaver techniques that overcome the limitations of conventional convolutional interleavers are desirable.